View V3021_57894.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

R
EM MICROELECTRONIC-MARIN SA
V3021
Ultra Low Power 1-Bit 32 kHz RTC
Features
n n n n n n n n n n n n n n Supply current typically 800 nA at 3 V 50 ns access time with 50 pF load capacitance Fully operational from 2.0 V to 5.5 V No busy states or danger of a clock update while accessing Serial communication on one line of a standard parallel data bus or over a conventional 3 wire serial interface Interface compatible with both Intel and Motorola Seconds, minutes, hours, day of month, month, year, week day and week number in BCD format Leap year and week number correction Time set lock mode to prevent unauthorized setting of the current time or date Oscillator stability 0.3 ppm / volt No external capacitor needed Frequency measurement and test modes Temperature range - 40 to +85 oC Packages DIP8 and SO8
Typical Operating Configuration
WR or R/W
RD or DS
CPU
Address Decoder
ADDRESS BUS
DATA BUS
CS RD WR I/O
XI XO
V3021
Description
The V3021 is a low power CMOS real time clock. Data is transmitted serially as 4 address bits and 8 data bits, over one line of a standard parallel data bus. The device is accessed by chip select (CS) with read and write control timing provided by either RD and WR pulse (Intel CPU) or DS with advanced R/W (Motorola CPU). Data can also be transmitted over a conventional 3 wire serial interface having CLK, data I/O and strobe. The V3021 has no busy states and there is no danger of a clock update while accessing. Supply current is typically 800 nA at VDD = 3.0 V. Battery operation is supported by complete functionality down to 2.0 V. The oscillator stability is typically 0.3 ppm/V. XI XO CS VSS
CS RD WR
RAM
Fig. 1
Pin Assignment
DIP8 / SO8
Applications
n n n n n n n n n n Utility meters Battery operated and portable equipment Consumer electronics White/brown goods Pay phones Cash registers Personal computers Programmable controller systems Data loggers Automotive electronics
VDD
V3021
WR RD I/O
Fig. 2
1
R
V3021
Absolute Maximum Ratings
Parameter
Maximum voltage at VDD
Symbol Conditions
VSS + 7.0 V VSS - 0.3 V VDD + 0.3 V VSS - 0.3 V +150 OC -65 OC 1000 V 250 OC x 10 s Table 1
VDDmax VDDmin Minimum voltage at VDD Maximum voltage at any signal pin Vmax Minimum voltage at any signal pin Vmin Maximum storage temperature TSTOmax TSTOmin Minimum storage temperature Electrostatic discharge maximum VSmax to MIL-STD-883C method 3015 TSmax Maximum soldering conditions
be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter Operating temperature Logic supply voltage Supply voltage dv/dt (power-up & power-down) Decoupling capacitor Crystal Characteristics 1) Frequency Load capacitance Series resistance
1)
Symbol Min. Typ . Max. Units TA VDD -40 2.0 +85 5.0 5.5 6 100 f CL RS 32.768 8.2 30 35 50
O
C V
Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
V/ms nF kHz pF kW Table 2
7
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, it is advised that normal precautions
See Fig. 3
Electrical Characteristics
VDD = 5.0V 10%, VSS = 0 V and TA = - 40 to 85 OC, unless otherwise specified Parameter Total static supply Total static supply Symbol ISS ISS Test Conditions all outputs open, all inputs at VDD VDD = 3.0 V, address 0 = 0 all outputs open, all inputs at VDD, VDD = 5 V, address 0 = 0 TA = +25OC I/O to VSS through 1 MW RD = VSS, WR = VDD, CS = 4 MHz address 0 = 0, read all 0 Min. Typ. 0.8 1.3 Max. 1.8 10 3 300 Units mA mA mA mA
Dynamic current
ISS
Input / Output Input logic low Input logic high Output logic low Output logic high Input leakage Output tri-state leakage on I/O pin Oscillator Starting voltage Input capacitance on XI Output capacitance on XO Start-up time Frequency stability Frequency Measurement Mode Current source on I/O pin pulsed on/off @ 256 Hz
VIL VIH VOL VOH IIN ITS
1.0 3.5 IOL = 4 mA IOH = 4 mA 0.0 < VIN < 5.0 V CS high, and address 0, bit 0, low 0.4 2.4 0.1 0.1 1 1
V V V V mA mA
VSTA CIN COUT TSTA Df/f IONF
1.8 TA = +25 OC TA = +25 OC 2.0 VDD 5.5V , TA = +25 OC CS high, addr.0, bit 0, high VI/O = 1 V 10 13 9 1 0.3 25
0.5 60
V pF pF s ppm/V mA Table 3
2
R
V3021
The V3021 will run slightly too fast, in order to allow the user to adjust the frequency, depending on the mean operating temperature. This is made since the crystal adjustment can only work by lowering the frequency with an added capacitor between XO and VSS. The printed circuit capacitance has also to be taken in consideration. The V3021 in DIL8 package, running with an 8.2 pF crystal at room temperature, will be adjusted to better than 1 s/day with a 6.8 pF capacitor.
Typical Frequency on I/O Pin
DF [ppm] Fo
80
Address 10 hex = 00 hex
s/day
3
Quartz with 8.2 pF load capacitance
30
2
-20
1
-70
0
-120
-1
-170 -50
-2 -30 -10 10 30 50 70 90 0 3 6 9 12 15
TA [O C] Typical drift for ideal 32'768 Hz quartz
External trimming capacitor between XO and VSS [pF] Note : The trimming capacitor value must not exceed 15 pF. Greater values may disturb the oscillator function. Fig. 3
Quartz Characteristics
DF F0 [ppm] DF ppm 2 Fo = - 0.038 OC2 (T - TO) 10% DF/Fo = the ratio of the change in frequency to the nominal value expressed in ppm (It can be thought of as the frequency deviation at any temperature.) = the temperature of interest in OC T = the turnover temperature (25 5 OC) TO To determine the clock error (accuracy) at a given temperature, add the frequency tolerance at 25OC to the value obtained from the formula above.
TO-100 TO-50 TO
O
Frequency ratio [ppm]
-100
ma x.
-200
-300
-400 TO+50 TO+100
min .
Temperature [ C]
T [OC] Fig. 4
3
R
V3021
Timing Characteristics
VSS = 0 V, and TA = - 40 to +85 OC, unless otherwise specified
Parameter
Symbol
tCS tACC tW tR tF tDF tDW tDH tADW tWC
Test Conditions
Min.
200
Max.
Min.
Typ.
Max.
Units
VDD 2 V Chip select duration 1) RAM access time Time between two transfers 2) Rise time 2) Fall time 3) Data valid to Hi-impedance 4) Write data settle time 5) Data hold time Advance write time 6) Write pulse time
1)
VDD = 5.0V 10%
50
50 60 200 200 40
Write cycle CLOAD = 50 pF
180
500 10 10 10 60 80 25 200
200 200 100
100 10 10 15 50 25 10 50
30
ns ns ns ns ns ns ns ns ns ns
Table 4
tACC starts from RD or CS, whichever activates last Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF 2) CS, RD, DS, WR and R/W rise and fall times are specified by tR and tF 3) tDF starts from RD or CS, whichever deactivates first 4) tDW ends at WR or CS, whichever deactivates first 5) tDH starts from WR or CS, whichever deactivates first 6) tWC starts from WR or CS, whichever activates last and ends at WR or CS, whichever deactivates first
Timing Waveforms
Read Timing for Intel (RD and WR Pulse) and Motorola (DS (or RD pin tied to CS) and R/W)
tCS CS tACC RD / DS WR / R/W tDF I/O data valid Fig. 5a tR tW tF
Write Timing for Intel (RD and WR Pulse)
tCS CS RD tWC WR tDW I/O data valid Fig. 5b tDH tW
4
R
V3021
Write Timing for Motorola (DS (or RD pin tied to CS) and R/W)
tCS CS DS R/W tDW I/O data valid tDH Fig. 5c tW
tADW
Communication Cycles
Read Data Cycle for Intel (RD and WR Pulse)
CS DS WR I/O
A0 A1 A2 A3 D0 D1 mP reads 8 data bits D7
mP writes 4 address bits
Fig. 6a
Read Data Cycle for Motorola (DS (or RD Pin Tied to CS) and R/W)
CS DS R/W I/O
A0 A1 A2 A3 D0 D1 mP reads 8 data bits D7
mP writes 4 address bits
Fig. 6b
Write Data Cycle for Intel (RD and WR Pulse)
CS RD " 1" " 0" WR I/O
A0 A1 A2 A3 D0 D1 mP reads 8 data bits D7
mP writes 4 address bits
Fig. 6c
5
R
V3021
Write Data Cycle for Motorola (DS (or RD Pin Tied to CS) and R/W)
CS DS R/W I/O
A0 A1 A2 A3 D0 D1 mP reads 8 data bits D7
mP writes 4 address bits
Fig. 6d Address Command Cycle for Intel (RD and WR Pulse)
CS RD WR I/O
A0 A1 A2 A3
Address Command Cycle for Motorola (DS (or RD Pin Tied to CS) and R/W)
CS
"1"
"0"
DS R/W I/O Fig. 6e
A0 A1 A2 A3
mP writes 4 address bits
mP writes 4 address bits
Fig. 6f
Block Diagram
XI XO Oscillator and Divider Chain 1Hz
Clock
(reserved area) 0 1 2 9
E F
Tue 2
mEM
Status 0 Status 1
RAM
(user RAM area)
Mon 1
mEM
Copy_RAM_to_clock Copy_clock_to_RAM
I/O CS
Read
Write
addr
data
Serial Buffer & Decoder
RD WR Fig. 7
6
R
V3021
Pin Description
Pin 1 2 3 4 5 6 7 8 Name XI XO CS VSS I/O RD WR VDD Function 32 kHz crystal input 32 kHz crystal output Chip select input Ground supply Data input and output Intel RD, Motorola DS (or tie to CS) Intel WR, Motorola R/W Positive supply Table 5
Address Command Cycle
An address command cycle consists of just 4 address bits. The LSB, A0, is transmitted first (see Fig. 6e and 6f). On writing the fourth address bit, A3, the address will be decoded. If the address bits are recognized as one of the command codes E hex or F hex (see Table 6), then the communication cycle is terminated and the corresponding command is executed. Subsequent microprocessor writes to the V3021 begin another communication cycle with the first bit being interpreted as the address LSB, A0.
Clock Configuration
The V3021 has a reserved clock area and a user RAM area (see Fig. 7). The clock is not directly accessible, it is used for internal time keeping and contains the current time and date. The contents of the RAM is shown in Table 6, it contains a data space and an address command space. The data space is directly accessible. Addresses 0 and 1 contain status information ( see Tables 7a and 7b), addresses 2 to 5, time data, and addresses 6 and 9, date data. The address command space is used to issue commands to the V3021.
Functional Description
Serial Communication
The V3021 resides on the parallel data and address buses as a standard peripheral (see Fig. 13 and 14). Address decoding provides an active low chip select (CS) to the device. For Intel compatible bus timing the control signals RD and WR pulse and CS are used for a single bit read or write (see Fig. 5a and 5b). Two options exist for Motorola compatible bus timing. The first is to use the control signals DS with R/W and CS, the second is to tie the RD input to CS and use the control signals R/W and CS (see Fig. 5a and 5c). Data transfer is accomplished through a single input / output line (I/O). Any data bus line can be chosen. A conventional 3 wire serial interface can also be used to communicate with the V3021 (see Fig. 15).
RAM Map Address Dec Hex Data Space
0 1 2 3 4 5 6 7 8 9 14 15 0 1 2 3 4 5 6 7 8 9 E F
Parameter
BCD range
Communication Cycles
The V3021 has 3 serial communication cycles. These are : 1) Read data cycle 2) Write data cycle 3) Address command cycle A communication cycle always begins by writing the 4 address bits, A0 to A3. A microprocessor read from the V3021 cannot begin a communication cycle. Read and write data cycles are similar and consist of 4 address bits and 8 data bits. The 4 address bits, A0 to A3, define the RAM location and the 8 data bits, D0 and D7, provide the relevant information. An address command cycle consists of only 4 address bits.
Status 0 Status 1 Seconds Minutes Hours Day of month Month Year Week day Week number Copy_RAM_to_clock Copy_clock_to_RAM
00-59 00-59 00-23 01-31 01-12 00-99 01-07 00-52
Address Command Space
Read Data Cycle
A read data cycle commences by writing the 4 RAM address bits (A3, A2, A1 and A0) to the V3021. The LSB, A0, is transmitted first (see Fig. 6a and 6b). Eight microprocessor reads from the V3021 will read the RAM data at this address, beginning with the LSB, D0. The read data cycle finishes on reading the 8th data bit, D7.
Table 6
Commands
Two commands are available (see Table 6). The Copy_RAM_to_clock command is used to set the current time and date in the clock and the Copy_clock_to_RAM command to copy the current time and date from the clock to the RAM. The Copy_RAM_to_clock command, address data E hex, causes the clock time and date to be overwritten by the time and date stored in the RAM at addresses 2 to 9. Address 1 is also cleared (see section "Time and Date Status Bits"). Prior to using this command, the desired time and date must be loaded into the RAM using write data cycles and the time set lock bit, address 0, bit 7, must be clear (see section " Time Set Lock").
Write Data Cycle
A write data cycle commences by writing the 4 RAM address bits (A3, A2, A1 and A0) to the V3021. The LSB, A0, is transmitted first (see Fig. 6c and 6d). Eight microprocessor writes to the V3021 will write the new RAM data. The LSB, D0, is loaded first. The write data cycle finishes on writing the 8th data bit, D7.
7
R
V3021
Status Information
The RAM addresses 0 and 1 contain status and control data for the V3021. The function of each bit (0 and 7) within address locations 0 and 1 is shown in Tables 7a and 7b respectively. On first startup or whenever power has failed (VDD < 2.0 V) the status register 0 and the clock must be initialized by software. Having initialized the interface to expect the address bit A0, write 0 to status register 0, then set the clock (see section "Clock and Calendar").
Status Word
Status 0 - address 0
76543210 Read / Write bits 0 - inactive 1 - active Frequency Measurement Mode Reserved Test Mode 0 Test Mode 1 Time Set Lock Reserved Reserved Reserved
Time and Date Status Bits
There are time and date status bits at address 1 in the RAM. Upon executing a Copy_clock_to_RAM command, the time and date status bits in the RAM show which time and date parameters changed since the last time this command was used. A logic 1 in the seconds status bit (address 1, bit 0) in the RAM indicates that the seconds location in the RAM (address 2) changed since the last Copy_clock_to_RAM command and thus needs to be read. The seconds location must change before any other time or date location can change. If the seconds status bit is clear, then no time or date location changed since the last Copy_clock_to_RAM command and so the RAM need not to be read by software. Table 7b shows the seconds, minutes, hours, day of the month, month, year, week day, and week number status bit locations. They are set or cleared similar to the seconds location. It should be noted that if the minutes status bit is clear, then the seconds bit may be set, but all other status bits are clear. Similarly with hours, the bits representing the units less than hours may have been set, but the bits for the higher units will be clear. This rule holds true for the week day or day of month locations also. The time and date status bits can be used to drive software routines which need to be executed every - second, - minute, - hour, - day of month / week day, - month, - year, or - week. In this application it is necessary to poll the V3021 at least once every time interval used as it does not generate an interrupt. Upon executing a Copy_RAM_to_clock command, the time and date status bits in the RAM are cleared.
Table 7a Status 1 - address 1
76543210 Read ONLY bits 0 - No change from last Copy_clock_to_RAM 1 - Change from last Copy_clock_to_RAM Seconds Minutes Hours Day of month Month Year Week day Week number
Table 7b
Reset and Initialization
Upon microprocessor recovery from a system reset, the V3021 must be initialized by software in order to guarantee that it is expecting a communication cycle (i.e the internal serial buffer is waiting for the address bit A0). Software can initialize the V3021 to expect a communication cycle by executing 8 microprocessor reads (see Fig. 8). Initializing Access to the V3021
Time Set Lock
The time set lock control bit is located at address 0, bit 4 (see Table 7a). When set by software, the bit disables the Copy_RAM_to_clock command (see section "Commands".) A set bit prevents unauthorized overwriting of the current time and date in the clock. Clearing the time set lock bit by software will re-enable the Copy_RAM_to_clock command. On first startup or whenever power has failed (VDD < 2.0 V), the time set lock bit must be setup by software.
CS RD WR I/O D0 D1 mP reads 8 times Fig. 8 D7
8
R
V3021
Reading the Current Time and Date
will indicate which time and date addresses changed since the last time the command was used (see Fig. 9). The time and date from the last Copy_clock_to_RAM command is held unchanged in the RAM, except when power (VDD) has failed totally. To change the current time and date in the clock, the desired time and date must first be written to the RAM, the time set lock bit cleared, and then a Copy_RAM_to_clock command sent (see Fig. 10). The time set lock bit can be used to prevent unauthorized setting of the clock.
Send copy_clock_to_RAM addr. F hex
Read time and data status bits, addr. 1
Setting the Current Time and Date
Is the seconds status bit set, addr. 1, bit 0
No Write seconds, minutes, hours, day of month, week day, month, year and week number to the RAM
Yes Read seconds, addr. 2 Clear the time set lock bit, addr. 0, bit 4
Send a copy_RAM_to_clock command, addr. E hex
Is the minutes status bit set, addr. 1, bit 1
No
Set the time set lock bit, addr. 0, bit 4
Fig. 10 Yes Read minutes addr. 3
Frequency Measurement
Setting bit 0 at address 0 will put a pulsed current source (25 mA) onto the I/O pin, when the device is not chip selected (i.e. CS input high). The current source will be pulsed on/off at 256 Hz. The period for 0 ppm time keeping is 3.90625 ms. To measure the frequency signal on pin I/O, the data bus must be high impedance. The best way to ensure this is to hold the microprocessor and peripherals in reset mode while measuring the frequency. The clarity of the signal measured at pin I/O will depend on both the probe input impedance (typically 1 MW) and the magnitude of the leakage current from other devices driving the line connected to pin I/O. If the signal measured is unclear, put a 200 kW resistor from pin I/O to VSS. It should be noted that the magnitude of the current source (25 mA) is not sufficient to drive the data bus line in case of any other device driving the line, but it is sufficient to take the line to a high logic level when the data bus is in high impedance. Use a crystal of nominal CL = 8.2 pF as specified in the section "Operating Conditions". The MX series from Microcrystal is recommended. The accuracy of the time keeping is dependent upon the frequency tolerance and the load capacitance of the crystal. 11.57 ppm correspond to one second a day.
Similar for hours, day of month, week day, month, year and week number
Current time and date Fig. 9
Clock and Calendar
The time and date addresses in the RAM (see Table 6) provide access to the seconds, minutes, hours, day of month, month, year, week day, and week number. These parameters have the ranges indicated on Table 6 and are in BCD format. If a parameter is found to be out of range, it will be cleared on its being next incremented. The V3021 incorporates leap year correction and week number calculation. The week number changes only at the incrementation of the day number from 7 to 1. If week 52 day 7 falls on the 25th, 26th or 27th of December, then the week number will change to 0 otherwise it will be week 1. Week days are numbered from 1 to 7 with Monday as 1. Reading of the current time and date must be preceded by a Copy_clock_to_RAM command. The time and date status bits
9
R
V3021
Test
From the various test features added to the V3021 some may be activated by the user. T able 7a shows the test mode bits. Table 8 shows the 3 available test modes and how they can be activated. Test mode 0 is activated by setting bit 2, address 0, and causes all time keeping to be accelerated by 32. Test mode 1 is activated by setting bit 3, address 0, and causes all the time and date locations, address 2 to address 9, to be incremented in parallel at 1 Hz with no carry over (independent of each other). The third test mode combines the previous two resulting in parallel incrementing at 32 Hz. XI 0 - 5.5 V 100 kW
1) 1)
V3021
XO
56 kW VSS
1)
indicative values
Fig. 11b
Test Modes Addr. 0 Addr. 0 bit 3 bit 2
0 0 1 1 0 1 0 1
Note : The peak value of the signal provided by the signal generator should not exceed 2 V on XO.
Function
Normal operation All time keeping accelerated by 32 Parallel increment of all time data at 1 Hz with no carry over Parallel increment of all time data at 32 Hz with no carry over Table 8
Crystal Layout
In order to ensure proper oscillator operation we recommend the following standard practices: - Keep traces as short as possible. - Use a guard ring around the crystal. Fig. 12 shows the recommended layout.
Oscillator Layout
An external signal generator can be used to drive the divider chain of the V3021. Fig. 11a and 11b show how to connect the signal generator. The speed can be increased by increasing the signal generator frequency to a maximum of 128 kHz. An external signal generator and test modes can be combined. To leave test both test bits (address 0, bits 2 and 3) must be cleared by software. Test corrupts the current time and date and so the time and date should be reloaded after a test session. CS Vss
XI
XO
V3021
Fig. 12
Signal Generator Connection
Access Considerations
The section "Communication Cycles" describes the serial data sequences necessary to complete a communication cycle. In common with all serial peripherals, the serial data sequences are not re-entrant, thus a high priority interrupt, or another software task, should not attempt to access the V3021 if it is already in the middle of a cycle. A semaphore (software flag) on access would allow the V3021 to be shared with other software tasks or interrupt routines. There is no time limit on the duration of a communication cycle and thus interrupt routines (which do not use the V3021) can be fully executed in mid cycle without any consequences for the V3021.
XI 1-2 V
peak to peak
V3021
XO
VSS Fig. 11a Note : The peak value of the signal provided by the signal generator should not exceed 2 V on XO.
10
R
V3021
Typical Applications
V3021 Interfaced with Intel CPU (RD/WR Pulse)
BUS A/D 0-7 D0 BUS ADDRESS A8-A15
8088
WR RD
Decoder
to other peripherals and memory
CS RD WR
I/O
V3021 Fig. 13
V3021 Interfaced with Motorola CPU (Advanced R/W)
BUS A/D 0-7 D0
68000
R/W LDS
BUS ADDRESS A8-A15 Decoder
to other peripherals and memory
CS RD WR
I/O
V3021 Fig. 14
3 Wire Serial Interface
P V3021
CLK DATA Strobe 1) & 2) RD I/O WR Port A.0 Port A.1 Port A.2 1) With strobe low bits are written to the V3021, and with strobe high bits are read from the V3021 2) For serial ports with byte transfer only, an address command cycle should be combined with every data cycle to give 8 address bits and 8 data bits. For example to read the current minutes, write address data F + 3 (1111 + 0011) and then read 8 data bits.
P
CS
VSS
CS
V3021
WR RD I/O
Fig. 15
Battery Switch Over Circuit
+5V BAT85* VDD 1MW BAT85* +5V
* Use Schottky barrier diodes. The BAT85 has a typical VF of 250 mV at an iF of 1 mA. The reverse current is typically 200 nA at a VR of 5 V. The reverse recovery time is 5 ns. For surface mount applications use the Philips BAT17 in SOT-23 or other.
V3021
+3 V
CS I/O VSS D0 of data bus
Motorola BS107A or 3N171
Fig. 16
11
R
V3021
Ordering Information
The V 3021 is available in the following package : DIP8 plastic package SO8 plastic package V3021 8P V3021 8S
When ordering, please specify the complete part number.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date
O 2000 EM Microelectronic-Marin SA, 10/00, Rev. K/331
EM MICROELECTRONIC-MARIN SA, CH-2074 Marin, Switzerland, Tel. +41 32 - 755 51 11, Fax +41 32 - 755 54 03
12

▲Up To Search▲

Price & Availability of V3021

	To Download V3021 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .